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Product Family: Low Power SRAM

Gain long term Low Power Asynchronous SRAM IC and KGD including 5V supply capability. A wide range of organizations for legacy replacement or new designs can be found by using our parametric tool.

Please use our Parametric Search Tool or alternatively select a product from the list below:

Available Products:

IS61LV256AL 256K Low-Voltage Asynchronous SRAM bare die configured as 32K x 8
IS61WV102416BLL 16M High-Speed Low-Power Aynchronous SRAM bare die with 3.3V supply configured as 1M x 16
IS61WV102416DBLL 16M High-Speed Low-Power Aynchronous SRAM bare die with 3.3V / 1.8V supply configured as 1M x 16
IS61WV20488BLL 16M High-Speed Low-Power Asynchronous SRAM bare die configured as 2M x 8
IS61WV25616BLL 4M High-Speed Low-Power Asynchronous SRAM bare die configured as 256K x 16
IS61WV25616BLS 4M High-Speed Low-Power Asynchronous SRAM bare die configured as 256K x 16
IS61WV25632BLL 8M High-Speed Low-Power Aynchronous SRAM bare die with 3.3V supply configured as 256K x 32
IS61WV51216EDBLL 8M High-Speed Low-Power Aynchronous SRAM bare die with on-chip ECC configured as 512K x 16
IS61WV51216EEBLL 8M High-Speed Low-Power Aynchronous SRAM bare die with on-chip ECC configured as 512K x 16
IS61WV5128BLL 4M High-Speed Low-Power Asynchronous SRAM bare die configured as 512K x 8
IS61WV6416BLL 1M High-Speed Low-Power Asynchronous SRAM bare die configured as 64K x 16
IS62C1024AL 1M Low Power Asynchronous SRAM bare die configured as 128K x 8
IS62WV102416BLL 16M High-Speed Low-Power Asynchronous SRAM bare die configured as 1M x 16
IS62WV10248BLL 8M High-Speed Ultra-Low-Power Asynchronous SRAM bare die configured as 1M x 8
S6L1008C The S6L1008C is a 1,048,576-bit high-speed Static Random Access Memory organized as 128K words by 8 bits. Designed for low power applications, these devices are well suited for battery back up and low data retention current requirements.
S6L1008W The S6L1008W is a 1,048,576-bit high-speed Static Random Access Memory organized as 128K words by 8 bits. Designed for low power applications, these devices are well suited for battery back up and low data retention current requirements.
S6L1016C 1,048,576-bit high-speed SRAM organized as 64K words by 16 bits. Designed for low power, these devices are well suited for battery back up and low data retention current requirements. Lower/upper byte access is set by data byte control select.
S6L1016W 1,048,576-bit high-speed SRAM organized as 64K words by 16 bits. Designed for low power, these devices are well suited for battery back up and low data retention current requirements. Lower/upper byte access is set by data byte control select.
S6L2008C The S6L2008C is a 2,097,152-bit high-speed Static Random Access Memory organized as 256K words by 8 bits. Designed for low power applications, these devices are well suited for battery back up and low data retention current requirements.
S6L2008W The S6L2008W is a 2,097,152-bit high-speed Static Random Access Memory organized as 256K words by 8 bits. Designed for low power applications, these devices are well suited for battery back up and low data retention current requirements.
S6L2016C 2,097,152-bit high-speed SRAM organized as 128K words by 16 bits. Designed for low power, these devices are well suited for battery back up and low data retention current requirements. Lower/upper byte access is set by data byte control select.
S6L2016W 2,097,152-bit high-speed SRAM organized as 128K words by 16 bits. Designed for low power, these devices are well suited for battery back up and low data retention current requirements. Lower/upper byte access is set by data byte control select.
S6L4008C The S6L4008C is a 4,194,304-bit high-speed Static Random Access Memory organized as 512K words by 8 bits. Designed for low power applications, these devices are well suited for battery back up and low data retention current requirements.
S6L4008W The S6L4008W is a 4,194,304-bit high-speed Static Random Access Memory organized as 512K words by 8 bits. Designed for low power applications, these devices are well suited for battery back up and low data retention current requirements.
S6L4016C 4,194,304-bit high-speed SRAM organized as 256K words by 16 bits. Designed for low power, these devices are well suited for battery back up and low data retention current requirements. Lower/upper byte access is set by data byte control select.
S6L4016W 4,194,304-bit high-speed SRAM organized as 256K words by 16 bits. Designed for low power, these devices are well suited for battery back up and low data retention current requirements. Lower/upper byte access is set by data byte control select.