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Product Family: High Speed SRAM

Gain long term support for High Speed Asynch SRAM IC and KGD including 5V. You can find a wide range of organizations for both legacy replacement and new designs by using our parametric tool.

Please use our Parametric Search Tool or alternatively select a product from the list below:

Available Products:

IS61C1024AL 1M High-Speed Asynchronous SRAM bare die configured as 128K x 8
IS61C25616AL 4M High-Speed Asynchronous SRAM bare die configured as 256K x 16
IS61C5128AL 4M High-Speed Asynchronous SRAM bare die configured as 512K x 8
IS61C6416AL 1M High-Speed Asynchronous SRAM bare die configured as 64K x 16
IS61LV256AL 256K Low-Voltage Asynchronous SRAM bare die configured as 32K x 8
IS61WV102416BLL 16M High-Speed Low-Power Aynchronous SRAM bare die with 3.3V supply configured as 1M x 16
IS61WV102416DBLL 16M High-Speed Low-Power Aynchronous SRAM bare die with 3.3V / 1.8V supply configured as 1M x 16
IS61WV20488BLL 16M High-Speed Low-Power Asynchronous SRAM bare die configured as 2M x 8
IS61WV25616BLL 4M High-Speed Low-Power Asynchronous SRAM bare die configured as 256K x 16
IS61WV25616BLS 4M High-Speed Low-Power Asynchronous SRAM bare die configured as 256K x 16
IS61WV25632BLL 8M High-Speed Low-Power Aynchronous SRAM bare die with 3.3V supply configured as 256K x 32
IS61WV51216EDBLL 8M High-Speed Low-Power Aynchronous SRAM bare die with on-chip ECC configured as 512K x 16
IS61WV51216EEBLL 8M High-Speed Low-Power Aynchronous SRAM bare die with on-chip ECC configured as 512K x 16
IS61WV5128BLL 4M High-Speed Low-Power Asynchronous SRAM bare die configured as 512K x 8
IS61WV6416BLL 1M High-Speed Low-Power Asynchronous SRAM bare die configured as 64K x 16
IS62C1024AL 1M Low Power Asynchronous SRAM bare die configured as 128K x 8
IS62WV102416BLL 16M High-Speed Low-Power Asynchronous SRAM bare die configured as 1M x 16
IS62WV10248BLL 8M High-Speed Ultra-Low-Power Asynchronous SRAM bare die configured as 1M x 8
S6R1008C1A The S6R1008C1A is a 1,048,576-bit high-speed Static Random Access Memory organized as 128k words by 8 bits. The S6R1008C1A uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.
S6R1008V1A The S6R1008V1A is a 1,048,576-bit high-speed Static Random Access Memory organized as 128k words by 8 bits. The S6R1008V1A uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.
S6R1008W1A The S6R1008W1A is a 1,048,576-bit high-speed Static Random Access Memory organized as 128k words by 8 bits. The S6R1008W1A uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.
S6R1016C1A 1,048,576-bit high-speed SRAM organized as 64k words by 16 bits. The device uses 16 common i/o lines & an output enable pin operating faster than address access time at read cycle. Lower/upper byte access is set by data byte control (NOT UB, NOT LB).
S6R1016V1A 1,048,576-bit high-speed SRAM organized as 64k words by 16 bits.The device uses 16 common i/o lines & an output enable pin operating faster than address access time at read cycle. Lower/upper byte access is set by data byte control (NOT UB, NOT LB).
S6R1016W1A 1,048,576-bit high-speed SRAM organized as 64k words by 16 bits. The device uses 16 common i/o lines & an output enable pin operating faster than address access time at read cycle. Lower/upper byte access is set by data byte control (NOT UB, NOT LB).
S6R1608C1M The S6R1608C1M is a 16,789,216-bit high-speed Static Random Access Memory organized as 2M words by 8 bits. The S6R1608C1M uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.
S6R1608V1M The S6R1608V1M is a 16,789,216-bit high-speed Static Random Access Memory organized as 2M words by 8 bits. The S6R1608V1M uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.
S6R1608W1M The S6R1608W1M is a 16,789,216-bit high-speed Static Random Access Memory organized as 2M words by 8 bits. The S6R1608W1M uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.
S6R1616C1M 16,789,216-bit high-speed SRAM organized as 1M words by 16 bits. The device uses 16 common i/o lines & an output enable pin operating faster than address access time at read cycle. Lower/upper byte access is set by data byte control (NOT UB, NOT LB).
S6R1616V1M 16,789,216-bit high-speed SRAM organized as 1M words by 16 bits.The device uses 16 common i/o lines & an output enable pin operating faster than address access time at read cycle. Lower/upper byte access is set by data byte control (NOT UB, NOT LB).
S6R1616W1M 16,789,216-bit high-speed SRAM organized as 1M words by 16 bits.The device uses 16 common i/o lines & an output enable pin operating faster than address access time at read cycle. Lower/upper byte access is set by data byte control (NOT UB, NOT LB).
S6R2008C1A The S6R2008C1A is a 2,097,152-bit high-speed Static Random Access Memory organized as 256k words by 8 bits. The S6R2008C1A uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.
S6R2008V1A The S6R2008V1A is a 2,097,152-bit high-speed Static Random Access Memory organized as 256k words by 8 bits. The S6R2008V1A uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.
S6R2008W1A The S6R2008W1A is a 2,097,152-bit high-speed Static Random Access Memory organized as 256k words by 8 bits. The S6R2008W1A uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.
S6R2016C1A 2,097,152-bit high-speed SRAM organized as 128k words by 16 bits.The device uses 16 common i/o lines & an output enable pin operating faster than address access time at read cycle. Lower/upper byte access is set by data byte control (NOT UB, NOT LB).
S6R2016V1A 2,097,152-bit high-speed SRAM organized as 128k words by 16 bits.The device uses 16 common i/o lines & an output enable pin operating faster than address access time at read cycle. Lower/upper byte access is set by data byte control (NOT UB, NOT LB).
S6R2016W1A 2,097,152-bit high-speed SRAM organized as 128k words by 16 bits.The device uses 16 common i/o lines & an output enable pin operating faster than address access time at read cycle. Lower/upper byte access is set by data byte control (NOT UB, NOT LB).
S6R4008C1A The S6R4008C1A is a 4,194,304-bit high-speed Static Random Access Memory organized as 512k words by 8 bits. The S6R4008C1A uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.
S6R4008V1A The S6R4008V1A is a 4,194,304-bit high-speed Static Random Access Memory organized as 512k words by 8 bits. The S6R4008V1A uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.
S6R4008W1A The S6R4008W1A is a 4,194,304-bit high-speed Static Random Access Memory organized as 512k words by 8 bits. The S6R4008W1A uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.
S6R4016C1A 4,194,304-bit high-speed SRAM organized as 256k words by 16 bits.The device uses 16 common i/o lines & an output enable pin operating faster than address access time at read cycle. Lower/upper byte access is set by data byte control (NOT UB, NOT LB).
S6R4016V1A 4,194,304-bit high-speed SRAM organized as 256k words by 16 bits.The device uses 16 common i/o lines & an output enable pin operating faster than address access time at read cycle. Lower/upper byte access is set by data byte control (NOT UB, NOT LB).
S6R4016W1A 4,194,304-bit high-speed SRAM organized as 256k words by 16 bits.The device uses 16 common i/o lines & an output enable pin operating faster than address access time at read cycle. Lower/upper byte access is set by data byte control (NOT UB, NOT LB).
S6R8008C1M The S6R8008C1M is a 8,388,608-bit high-speed Static Random Access Memory organized as 1M words by 8 bits. The S6R8008C1M uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.
S6R8008V1M The S6R8008V1M is a 8,388,608-bit high-speed Static Random Access Memory organized as 1M words by 8 bits. The S6R8008V1M uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.
S6R8008W1M The S6R8008W1M is a 8,388,608-bit high-speed Static Random Access Memory organized as 1M words by 8 bits. The S6R8008W1M uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.
S6R8016C1M 8,388,608-bit high-speed SRAM organized as 512k words by 16 bits.The device uses 16 common i/o lines & an output enable pin operating faster than address access time at read cycle. Lower/upper byte access is set by data byte control (NOT UB, NOT LB).
S6R8016V1M 8,388,608-bit high-speed SRAM organized as 512k words by 16 bits.The device uses 16 common i/o lines & an output enable pin operating faster than address access time at read cycle. Lower/upper byte access is set by data byte control (NOT UB, NOT LB).
S6R8016W1M 8,388,608-bit high-speed SRAM organized as 512k words by 16 bits.The device uses 16 common i/o lines & an output enable pin operating faster than address access time at read cycle. Lower/upper byte access is set by data byte control (NOT UB, NOT LB).