- Error detection and error correction
- Optional ERR1/ERR2 output pin
- ERR1 pin indicates 1-bit error detection and correction
- ERR2 pin indicates 2-bit error detection
- Better reliability than parity code schemes
- High-speed access time: 8,10 ns
- High performance, low power CMOS process
- 3-State outputs
- Committed long term support with very low obsolescence or mask change rate.
- Density: 8M
- Memory Cell: 6T
- ECC: Yes
VCC (Max): 3.60V
Speed: 8,10ns
ICC (Max) @ VNOM: 135mA
ISB(CMOS): 10.0mA
ISB(TTL): 50mA
- Density: 8M
- Memory Cell: 6T
- ECC: Yes
VCC (Max): 3.60V
Speed: 8,10ns
ISB: 10.000mA
ISB(Max): 50.000mA
ICC: n/a
ICC (Max) @ VNOM: 95mA
- Green:Available from stock or at low factory MOQ.
- Amber: Available on factory order with MOQ.
- Red: High factory MOQ may apply, please ask for details.
- Green: This bare die is specified and tested for use in high reliability applications.
- Amber: This bare die can meet higher reliability specifications with additional testing & qualification, please ask for details.
- Red: This bare die is not specified or specifically designed for use in high reliability applications.
- Green: This bare die is qualified for space applications or has space level qualification data, please ask for details.
- Amber: This bare die can be specified for space applications with additional testing and qualification, please ask for details.
- Red: Suitability of this bare die for space applications is unknown and requires further qualification, please ask for details.