Innovate > Integrate > Empower - Design at Die Level

  Back to List

Product Family: J-K Flip-Flop

Choose the right J-K Flip-Flop logic IC for your application by using our component parametric search and comparison tools.
Please use our Parametric Search Tool or alternatively select a product from the list below:

Available Products:

  • 54HC109   The 54HC109 is fabricated in 2.5µm 5V CMOS. The J and K logic level at the positive clock edge changes the device output state. Set & Reset functions are asynchronous, independent of clock & are executed by a logic low on the corresponding input.
  • 54HC112   The 54HC112 is fabricated in 2.5µm 5V CMOS. The J and K logic level at the negative clock edge changes the device output state. Set & Reset functions are asynchronous, independent of clock & are executed by a logic low on the corresponding input.
  • 74HC109   The 74HC109 is fabricated in 2.5µm 5V CMOS. The J and K logic level at the positive clock edge changes the device output state. Set & Reset functions are asynchronous, independent of clock & are executed by a logic low on the corresponding input.
  • 74HC112   The 74HC112 is fabricated in 2.5µm 5V CMOS. The J and K logic level at the negative clock edge changes the device output state. Set & Reset functions are asynchronous, independent of clock & are executed by a logic low on the corresponding input.
  • CD4027B   The CD4027B Dual J-K Master-Slave Flip-Flop consists of x2 identical complementary-symmetry J-K master-slave flip-flops. Each flip-flop is provisioned for individual J, K, Set Reset, & Clock input signals with buffered Q & Q \ output signals.
  • CD4027B   CMOS Dual J-K Master-Slave Flip-Flop
  • CD74AC109   Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset
  • CD74AC112   Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset
  • CD74ACT109   Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset
  • CD74ACT112   Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset
  • CD74HC107   High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset
  • CD74HC109   High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset
  • CD74HC112   High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset
  • CD74HC73   High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset
  • CD74HCT107   High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset
  • CD74HCT109   High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset
  • CD74HCT112   High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset
  • CD74HCT73   High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset
  • SN74ALS109A   Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset
  • SN74ALS112A   Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset
  • SN74AS109A   Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset
  • SN74F109   Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset
  • SN74F112   Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset
  • SN74HC109   Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset
  • SN74HC112   Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset
  • SN74LS107A   Dual J-K Flip-Flops With Clear
  • SN74LS109A   Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset
  • SN74LS112A   Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset
  • SN74LS73A   Dual J-K Flip-Flops with Clear
  • SN74LVC112A   Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset
  • SN74S112A   Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset