Bare Die Product Detail: SN74HC112

J-K Flip-Flop:
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset

Features:

Family: HC
Voltage(s) (Nom): 3.3, 5V
tpd @ Nom Voltage(s) : 41ns
Output Drive I_OL/I_OH (Max): -4/4mA
Output: 2S
th: 0ns
tsu: 21ns

Vendor:
Texas Instruments
Electrical Datasheet

Die Physical Data:
Footprint: 2.276mm² (3528mil²)
Request Pad Layout

Product Families: Used for this device are tabulated below.

J-K Flip-Flop

Functional:

Bits: 2
I/P Level: CMOS/LVTTL
O/P Level: CMOS

Specification:

V_{CC (Min)}: 2.00V
V_{CC (Max)}: 6.00V
f_MIN @ V_NOM: 70MHz
I_{CC (Max)} @ V_NOM: 0.040mA
V_{NOM (Max)}: 5.0V
Output Drive _(Max): 4.0mA
t_{pd (Max)} @ V_NOM: 41.0ns

Other Detail: Important information for this device is tabulated below.

Traffic light setting for Minimum Order Quantity indicates the following:

Green:Available from stock or at low factory MOQ.
Amber: Available on factory order with MOQ.
Red: High factory MOQ may apply, please ask for details.

Traffic light setting for High Reliability indicates the following:

Green: This bare die is specified and tested for use in high reliability applications.
Amber: This bare die can meet higher reliability specifications with additional testing & qualification, please ask for details.
Red: This bare die is not specified or specifically designed for use in high reliability applications.

Traffic light setting for Space Grade indicates the following:

Green: This bare die is qualified for space applications or has space level qualification data, please ask for details.
Amber: This bare die can be specified for space applications with additional testing and qualification, please ask for details.
Red: Suitability of this bare die for space applications is unknown and requires further qualification, please ask for details.