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Bare Die Product Detail: CD74AC112

J-K Flip-Flop:
Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset
Features:
  • Family:  AC
  • Voltage(s) (Nom):  3.3, 5V
  • tpd @ Nom Voltage(s) :  11.1ns
  • Output Drive IOL/IOH (Max):  -24/24mA
Vendor:
Texas Instruments
  Electrical Datasheet

Die Physical Data:
Footprint: 3.055mm² (4736mil²)
  Request Pad Layout
Product Families: Used for this device are tabulated below.
Functional:
  • Bits: 2
  • I/P Level: CMOS/LVTTL
  • O/P Level: CMOS
Specification:
VCC (Min): 1.50V
VCC (Max): 5.50V
fMIN @ VNOM: 100MHz
ICC (Max) @ VNOM: 0.040mA
VNOM (Max): 5.0V
Output Drive (Max): 24.0mA
tpd (Max) @ VNOM: 11.1ns
Other Detail: Important information for this device is tabulated below.
Traffic light setting for Minimum Order Quantity indicates the following:
  • Green:Available from stock or at low factory MOQ.
  • Amber: Available on factory order with MOQ.
  • Red: High factory MOQ may apply, please ask for details.
Traffic light setting for High Reliability indicates the following:
  • Green: This bare die is specified and tested for use in high reliability applications.
  • Amber: This bare die can meet higher reliability specifications with additional testing & qualification, please ask for details.
  • Red: This bare die is not specified or specifically designed for use in high reliability applications.
Traffic light setting for Space Grade indicates the following:
  • Green: This bare die is qualified for space applications or has space level qualification data, please ask for details.
  • Amber: This bare die can be specified for space applications with additional testing and qualification, please ask for details.
  • Red: Suitability of this bare die for space applications is unknown and requires further qualification, please ask for details.

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