Bare Die Product Detail: CDC582

Zero Delay Clock Buffer:
3.3V PLL Clock Driver with LVPECL Output & LVTTL Outputs with 1/2x, 1x and 2x Frequency Options

Features:
N/A

Vendor:
Texas Instruments
Electrical Datasheet

Die Physical Data:
Footprint: 7.246mm² (11232mil²)
Request Pad Layout

Product Families: Used for this device are tabulated below.

Functional:

Specification:

f_(MAX): 100MHz
Frequency _(MAX): 25MHz
Absolute Jitter: 200ps
Output Drive _(Max): 32mA
t_{sk (OUT)}: 500ps
t_{(phase error)}: 500ps

Functional:

Specification:

f_(MAX): 100MHz
Frequency _(MAX): 25MHz
Absolute Jitter: 200ps
Output Drive _(Max): 32mA
t_{sk (OUT)}: 500ps
t_{(phase error)}: 500ps

Other Detail: Important information for this device is tabulated below.

Traffic light setting for Minimum Order Quantity indicates the following:

Traffic light setting for High Reliability indicates the following:

Green: This bare die is specified and tested for use in high reliability applications.
Amber: This bare die can meet higher reliability specifications with additional testing & qualification, please ask for details.
Red: This bare die is not specified or specifically designed for use in high reliability applications.

Traffic light setting for Space Grade indicates the following:

Green: This bare die is qualified for space applications or has space level qualification data, please ask for details.
Amber: This bare die can be specified for space applications with additional testing and qualification, please ask for details.
Red: Suitability of this bare die for space applications is unknown and requires further qualification, please ask for details.