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Bare Die Product Detail: ADS808 REV 2

High Speed ADC (>10MSPS):
12-Bit, 70 MSPS ADC SE/Diff, Int/Ext Ref., Flexible Clocking, Selectable Fullscale Range & Powerdown
Features:
  • Architecture:  Pipeline
  • Input Buffer:  No
  • Reference Mode:  Ext, Int
  • DNL±(Max):  1.7LSB
  • Digital Supply(Min):  3V
  • Digital Supply(Max):  5V
Vendor:
Texas Instruments
  Electrical Datasheet

Die Physical Data:
Footprint: 16.721mm² (25917mil²)
  Request Pad Layout
Product Families: Used for this device are tabulated below.
Functional:
  • Bits: 12
  • Channels: 1
  • Interface: Par CMOS
Specification:
PC(Max): 720mW
AVDD (Min): 4.75V
AVDD (Max): 5.25V
SNR: 64.0dB
INL(Max): 4.0±LSB
SR(Max): 70MSPS
SFDR: 68.0dB
SINAD: 64.0dB
VIN: 2.00Vp-p
ENOB: 0.70Bits
Input BW: 1,000MHz
Other Detail: Important information for this device is tabulated below.
Traffic light setting for Minimum Order Quantity indicates the following:
  • Green:Available from stock or at low factory MOQ.
  • Amber: Available on factory order with MOQ.
  • Red: High factory MOQ may apply, please ask for details.
Traffic light setting for High Reliability indicates the following:
  • Green: This bare die is specified and tested for use in high reliability applications.
  • Amber: This bare die can meet higher reliability specifications with additional testing & qualification, please ask for details.
  • Red: This bare die is not specified or specifically designed for use in high reliability applications.
Traffic light setting for Space Grade indicates the following:
  • Green: This bare die is qualified for space applications or has space level qualification data, please ask for details.
  • Amber: This bare die can be specified for space applications with additional testing and qualification, please ask for details.
  • Red: Suitability of this bare die for space applications is unknown and requires further qualification, please ask for details.

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