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Bare Die Product Detail: CDCU877

Zero Delay Clock Buffer:
1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications
Features:
N/A
Vendor:
Texas Instruments
  Electrical Datasheet

Die Physical Data:
Footprint: 2.810mm² (4356mil²)
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Product Families: Used for this device are tabulated below.
Functional:
  • Outputs: 10
  • VCC: 1.8V
Specification:
f(MAX): 340MHz
Frequency (MAX): 10MHz
Absolute Jitter: 30ps
Output Drive (Max): 9mA
tsk (OUT): 35ps
t(phase error): 50ps
Functional:
  • Outputs: 10
  • VCC: 1.8V
Specification:
f(MAX): 340MHz
Frequency (MAX): 10MHz
Absolute Jitter: 30ps
Output Drive (Max): 9mA
tsk (OUT): 35ps
t(phase error): 50ps
Other Detail: Important information for this device is tabulated below.
Traffic light setting for Minimum Order Quantity indicates the following:
  • Green:Available from stock or at low factory MOQ.
  • Amber: Available on factory order with MOQ.
  • Red: High factory MOQ may apply, please ask for details.
Traffic light setting for High Reliability indicates the following:
  • Green: This bare die is specified and tested for use in high reliability applications.
  • Amber: This bare die can meet higher reliability specifications with additional testing & qualification, please ask for details.
  • Red: This bare die is not specified or specifically designed for use in high reliability applications.
Traffic light setting for Space Grade indicates the following:
  • Green: This bare die is qualified for space applications or has space level qualification data, please ask for details.
  • Amber: This bare die can be specified for space applications with additional testing and qualification, please ask for details.
  • Red: Suitability of this bare die for space applications is unknown and requires further qualification, please ask for details.

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