Bare Die Product Detail: CDCM7005

Single-Loop PLL Jitter Cleaner:
High Performance, Low Phase Noise, Low Skew Clock Synchronizer that Synchronizes Ref Clock to VCXO

Features:

Vendor:
Texas Instruments
Electrical Datasheet

Die Physical Data:
Footprint: 6.712mm² (10404mil²)
Request Pad Layout

Product Families: Used for this device are tabulated below.

Functional:

Specification:

V_{S (Min)}: 3.00V
V_{S (Max)}: 3.60V
f_{MAX (OUT)}: 1,500MHz

Functional:

Specification:

V_{S (Min)}: 3.00V
V_{S (Max)}: 3.60V
f_{MAX (IN)}: n/a
f_{MAX (OUT)}: 1,500MHz
Additive RMS Jitter: n/a
RMS Jitter: n/a

Functional:

Specification:

V_{S (Min)}: 3.00V
V_{S (Max)}: 3.60V
f_{MAX (IN)}: n/a
f_{MAX (OUT)}: 1,500MHz
Additive RMS Jitter: n/a
RMS Jitter: n/a

Other Detail: Important information for this device is tabulated below.

Traffic light setting for Minimum Order Quantity indicates the following:

Traffic light setting for High Reliability indicates the following:

Green: This bare die is specified and tested for use in high reliability applications.
Amber: This bare die can meet higher reliability specifications with additional testing & qualification, please ask for details.
Red: This bare die is not specified or specifically designed for use in high reliability applications.

Traffic light setting for Space Grade indicates the following:

Green: This bare die is qualified for space applications or has space level qualification data, please ask for details.
Amber: This bare die can be specified for space applications with additional testing and qualification, please ask for details.
Red: Suitability of this bare die for space applications is unknown and requires further qualification, please ask for details.